Report a bug
If you spot a problem with this page, click here to create a Bugzilla issue.
Improve this page
Quickly fork, edit online, and submit a pull request for this page.
Requires a signed-in GitHub account. This works well for small changes.
If you'd like to make larger changes you may want to consider using
a local clone.
core.cpuid
Identify the characteristics of the host CPU, providing information
about cache sizes and assembly optimisation hints. This module is
provided primarily for assembly language programmers.
References: Some of this information was extremely difficult to track down. Some of the documents below were found only in cached versions stored by search engines! This code relies on information found in:
- "Intel(R) 64 and IA-32 Architectures Software Developers Manual, Volume 2A: Instruction Set Reference, A-M" (2007).
- "AMD CPUID Specification", Advanced Micro Devices, Rev 2.28 (2008).
- "AMD Processor Recognition Application Note For Processors Prior to AMD Family 0Fh Processors", Advanced Micro Devices, Rev 3.13 (2005).
- "AMD Geode(TM) GX Processors Data Book", Advanced Micro Devices, Publication ID 31505E, (2005).
- "AMD K6 Processor Code Optimisation", Advanced Micro Devices, Rev D (2000).
- "Application note 106: Software Customization for the 6x86 Family", Cyrix Corporation, Rev 1.5 (1998)
- http://www.datasheetcatalog.org/datasheet/nationalsemiconductor/GX1.pdf
- "Geode(TM) GX1 Processor Series Low Power Integrated X86 Solution", National Semiconductor, (2002)
- "The VIA Isaiah Architecture", G. Glenn Henry, Centaur Technology, Inc (2008).
- http://www.sandpile.org/ia32/cpuid.htm
- http://www.akkadia.org/drepper/cpumemory.pdf
- "What every programmer should know about memory", Ulrich Depper, Red Hat, Inc., (2007).
- "CPU Identification by the Windows Kernel", G. Chappell (2009). http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm
- "Intel(R) Processor Identification and the CPUID Instruction, Application Note 485" (2009).
Bugs:
Currently only works on x86 and Itanium CPUs.
Many processors have bugs in their microcode for the CPUID instruction,
so sometimes the cache information may be incorrect.
License:
Authors:
Don Clugston, Tomas Lindquist Olsen <[email protected]>
Source: core/cpuid.d
- Cache size and behaviour
- Size of the cache, in kilobytes, per CPU.
-
- 1 = direct mapped
- 2 = 2-way set associative
- 3 = 3-way set associative
- ubyte.max = fully associative
- Number of bytes read into the cache when a cache miss occurs.
- Scheduled for deprecation. Please use dataCaches instead.
- The data caches. If there are fewer than 5 physical caches levels,the remaining levels are set to size_t.max (== entire memory space)
-
Do NOT use this to determine features! Note that some CPUs have programmable vendorIDs.
- Does it have an x87 FPU on-chip?
- Is MMX supported?
- Is SSE supported?
- Is SSE2 supported?
- Is SSE3 supported?
- Is SSSE3 supported?
- Is SSE4.1 supported?
- Is SSE4.2 supported?
- Is SSE4a supported?
- Is AES supported
- Is pclmulqdq supported
- Is rdrand supported
- Is AVX supported
- Is VEX-Encoded AES supported
- Is vpclmulqdq supported
- Is FMA supported
- Is FP16C supported
- Is AVX2 supported
- Is HLE (hardware lock elision) supported
- Is RTM (restricted transactional memory) supported
- Is rdseed supported
- Is SHA supported
- Is AMD 3DNOW supported?
- Is AMD 3DNOW Ext supported?
- Are AMD extensions to MMX supported?
- Is fxsave/fxrstor supported?
- Is cmov supported?
- Is rdtsc supported?
- Is cmpxchg8b supported?
- Is cmpxchg8b supported?
- Is SYSENTER/SYSEXIT supported?
- Is 3DNow prefetch supported?
- Are LAHF and SAHF supported in 64-bit mode?
- Is POPCNT supported?
- Is LZCNT supported?
- Is this an Intel64 or AMD 64?
- Is this an IA64 (Itanium) processor?
- Is hyperthreading supported?
- Returns number of threads per CPU
- Returns number of cores in CPU
- Optimisation hints for assembly code.For forward compatibility, the CPU is compared against different microarchitectures. For 32-bit x86, comparisons are made against the Intel PPro/PII/PIII/PM family. The major 32-bit x86 microarchitecture 'dynasties' have been:
- Intel P6 (PentiumPro, PII, PIII, PM, Core, Core2).
- AMD Athlon (K7, K8, K10).
- Intel NetBurst (Pentium 4, Pentium D).
- In-order Pentium (Pentium1, PMMX, Atom)
- Intel Atom 230/330 (family 6, model 0x1C) is an in-order core.
- Centaur Isiah = VIA Nano (family 6, model F) is an out-of-order core.
- Does this CPU perform better on Pentium4 code than PentiumPro..Core2 code?
- Does this CPU perform better on Pentium I code than Pentium Pro code?
- Warning: This field will be turned into a property in a future release.Processor type (vendor-dependent). This should be visible ONLY for display purposes.
- Warning: This field will be turned into a property in a future release.Processor type (vendor-dependent). This should be visible ONLY for display purposes.
- Warning: This field will be turned into a property in a future release.Processor type (vendor-dependent). This should be visible ONLY for display purposes.
- This field has been deprecated. Please use cacheLevels instead.
- The number of cache levels in the CPU.
Copyright Don Clugston 2007 - 2009.
| Page generated by
Ddoc on (no date time)